The present invention relates to a system for testing an electronic counter with carry inputs and, more particularly, to a system for testing operation of an entire counter by testing operation of sections thereof.
In the field of data processing and in other electronic fields, counting devices are used extensively for timing and other accounting activities. Such counting devices can have a plurality of values, dependent upon the number of bits that the counter is capable of storing. It is often necessary to test counters for proper operation. Counters and other components are generally tested before shipment to a customer but can also be tested by the customer upon delivery of the electronic equipment.
Testing of counting devices is especially important to ensure proper carry operation during incrementing. That is, when a binary 1 is added to a binary 1 already loaded in a given bit location, the next significant bit must be incremented as a result of a carry thereto.
It is important to determine whether every bit of a counter can toggle properly. If a bit is stuck at zero, for example, then obviously operation of the entire counter is suspect.
Traditionally, every value of which a counter is capable of storing is tested individually and sequentially. This has been a time consuming process. For example, if a counter has 22 bits, the testing operation must be performed for each of 2.sup.22 combinations to ensure that all values have been properly tested and that all bits have been evaluated for toggling as a consequence of the natural carry process. Such testing is usually performed sequentially from the lowest value of the counter (all zeroes) to the highest (all ones).
One prior art solution to the problem of testing a counter without incrementing through all of its values is to load predetermined addresses, the incrementation of which would force a carry for specified bits. For example, in a 6-bit counter, the value 000111 could be loaded into the counter and then incremented by one. This would result in a carry over of the third bit (from the right side) to the fourth bit, resulting in the value 001000. Such prior art systems are generally not cost effective, as they require sophisticated programming and logic to load the predetermined values required to test toggling of all natural carry bits. A complete test requires determination that all of the bits dependent upon previous bits toggle properly and that each bit individually can toggle properly from low to high and from high to low.
It should be appreciated that often many relatively large counters are present in an integrated circuit chip and that a great number of integrated circuit chips are used in larger systems. Thus, the amount of time spent testing systems is directly dependent on, inter alia, the time it takes to test a counter thoroughly.
It would be advantageous to provide a testing process for a counter that would work efficiently and quickly.
It would also be advantageous to provide a testing system for a counter that would require generally unsophisticated logic circuitry.
It would also be advantageous to provide a counter tester that would operate in less time than conventional testers which require sequential accessing of every value in the counter.
It would also be advantageous to provide a system that requires minimal programming of test bits to test the counter completely.